Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1a, a memory device such as a flash memory 10 comprises one or more high density core regions 11 and a low density peripheral portion 12 on a single substrate 13. The high density core regions 11 typically consist of at least one M.times.N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion 12 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion 11 are coupled together in a NAND-type circuit configuration, such as, for example, the configuration illustrated in prior art FIG. 1b. Each memory cell 14 has a drain 14a, a source 14b and a stacked gate 14c. A plurality of memory cells 14 connected together in series with a drain select transistor at one end and a source select transistor at the other end to form a NAND string as illustrated in prior art FIG. b. Each stacked gate 14c is coupled to a word line (WL0, WL1 , . . . , WLn) while each drain of the drain select transistors are coupled to a bit line (BL0, BL1, . . . , BLn). Lastly, each source of the source select transistors are coupled to a common source line Vss. Using peripheral decoder and control circuitry, each memory cell 14 can be addressed for programming, reading or erasing functions.
Prior art FIG. 1c represents a fragmentary cross section diagram of a typical memory cell 14 in the core region 11 of prior art FIGS. 1a and 1b. Such a cell 14 typically includes the source 14b, the drain 14a and a channel 15 in a substrate or P-well 16; and the stacked gate structure 14c overlying the channel 15. The stacked gate 14c further includes a thin gate dielectric layer 17a (commonly referred to as the tunnel oxide) formed on the surface of the P-well 16. The stacked gate 14c also includes a polysilicon floating gate 17b which overlies the tunnel oxide 17a and an interpoly dielectric layer 17c overlies the floating gate 17b. The interpoly dielectric layer 17c is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate 17d overlies the interpoly dielectric layer 17c. The control gates 17d of the respective cells 14 that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, for example, prior art FIG. 1b). In addition, as highlighted above, the drain regions 14a of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel 15 of the cell 14 conducts current between the source 14b and the drain 14a in accordance with an electric field developed in the channel 15 by the stacked gate structure 14c.
The select transistors have a stacked gated structure similar to the memory cells, except that the first polysilicon layer (floating gate) and the second polysilicon layers (control gate) are shorted together to form a single gate type structure. Select gates typically ensure the selectivity of a particular bit line and prevent the memory cells from passing current during the program operation.
A poly 1 contact is made to the first polysilicon gate of the select transistor while a poly 2 contact is made to the tungsten silicide/second polysilicon gate (control gate) of the memory cells. These contacts are typically formed through an oxide layer covering the memory cells and select transistors (a so-called interlayer dielectric). These contacts are also typically formed at about the same time (or during the same processing window). However, while the depth of the poly 2 contact is smaller than the depth of the poly 1 contact, the time required to form an high quality poly 2 contact is undesirably greater than the amount of time required to form a poly 1 contact.
This phenomenon leads to deleterious overetching of the poly 1 layer (first polysilicon layer). In some instances, the overetching is severe enough that the poly 1 contact opening extends into the field oxide and/or even into the substrate. Such overetching is termed punch-through. Poly 1 contact punch-through renders the select gate inoperable, consequently resulting in failure of the flash memory device. In instances where the overetching is not so severe (where the poly 1 contact opening extends deep into the first polysilicon layer, but not completely through), there is a resultant increase in poly 1 contact resistivity. Increases in poly 1 contact resistivity can lead to parametric failure of the flash memory device, and/or latent reliability problems since the increased contact resistivity often leads to thermal heating, which, in turn, further increases the resistivity often leading to device failure.
Attempts to address punch-through involve making the first polysilicon layer thicker. But the thicker the first polysilicon layer, the more likely undesirable cracking occurs in the tungsten silicide layer and the more likely etch problems occur due to high aspect ratios and high topographies. Moreover, there are numerous other concerns associated with setting the thickness of the first polysilicon layer. For example, the thicker the floating gate, the higher the stress released on the tunnel oxide layer, improving tunnel oxide reliability, improving conductivity and thus resulting in better circuit performance. The thinner the floating gate, the more likely an increase in pinhole defects. Further, when the thickness of the Poly 1 is too thin, an HF dip cleaning step (prior to forming the ONO multilayer dielectric film) may degrade the Poly 1 and attack the tunnel oxide. Therefore, it is desirable to set the thickness of the first polysilicon layer without regard to punch-through problems, since there are other important concerns to address. It is also desirable, nevertheless to address the undesirable punch-through problem.